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M68AF127B
1Mbit (128K x8), 5V Asynchronous SRAM
FEATURES SUMMARY

SUPPLY VOLTAGE: 4.5 to 5.5V 128K x 8 bits SRAM with OUTPUT ENABLE EQUAL CYCLE and ACCESS TIMES: 55ns LOW STANDBY CURRENT LOW VCC DATA RETENTION: 2V TRI-STATE COMMON I/O LOW ACTIVE and STANDBY POWER
Figure 1. Packages
SO32 (MC)
32
1
PDIP32 (B)
TSOP32 (NK) 8 x 13.4mm
TSOP32 (N) 8 x 20mm
September 2004
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M68AF127B
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 TABLE OF CONTENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Table 1. Figure 3. Figure 4. Figure 5. Figure 6. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 SO Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 4. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 7. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 8. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 5. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 9. Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 10.Chip Enable or Output Enable Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . 11 Figure 11.Chip Enable Controlled, Standby Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 12.Write Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 13.Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 14.E1 Controlled, Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 15.E2 Controlled, Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 9. Low VCC Data Retention Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 16.SO32 - 32 lead Plastic Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 10. SO32 - 32 lead Plastic Small Outline, Package Mechanical Data. . . . . . . . . . . . . . . . . . 17 Figure 17.PDIP32 - 32 pin Plastic DIP, 600 mils width, Package Outline . . . . . . . . . . . . . . . . . . . . 18 Table 11. PDIP32 - 32 pin Plastic DIP, 600 mils width, Package Mechanical Data . . . . . . . . . . . . 18 Figure 18.TSOP32 - 32-lead Thin Small Outline Package, 8x13.4mm, Package Outline . . . . . . . . 19
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M68AF127B
Table 12. TSOP32 - 32-lead Thin Small Outline Package, 8x13.4mm, Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 19.TSOP32 - 32 lead Plastic Thin Small Outline, 8x20mm, Package Outline . . . . . . . . . . . 20 Table 13. TSOP32 - 32 lead Plastic Thin Small Outline, 8x20mm, Package Mechanical Data . . . 20 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 14. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 15. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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M68AF127B
SUMMARY DESCRIPTION
The M68AF127B is a 1Mbit (1,048,576 bit) CMOS SRAM, organized as 131,072 words by 8 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 4.5 to 5.5V supply. This device has an automatic power-down feature, reducing the power consumption by over 99% when deselected. The M68AF127B is available in SO32, PDIP32, TSOP32 (8x13.4mm) and TSOP32 (8x20mm) packages.
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A16 DQ0-DQ7 Address Inputs Data Input/Output Chip Enable Chip Enable Output Enable Write Enable Supply Voltage Ground
VCC
E1 E2
17 A0-A16
8 DQ0-DQ7
G W
W E1 E2 G M68AF127B
VCC VSS
VSS
AI05472B
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M68AF127B
Figure 3. SO Connections Figure 5. TSOP Connections
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1
32
8 9
M68AF127B
25 24
16
17
AI07270B
VCC A15 E2 W A13 A8 A9 A11 G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3
A11 A9 A8 A13 W E2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4
1
32
8 9
M68AF127B
25 24
16
17
AI05473d
G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
Figure 4. DIP Connections
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 2 3 4 5 6 7 8 M68AF127B 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC A15 E2 W A13 A8 A9 A11 G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3
AI07203B
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M68AF127B
Figure 6. Block Diagram
A16 ROW DECODER A7 MEMORY ARRAY
DQ7
I/O CIRCUITS COLUMN DECODER
DQ0 E1 E2 A0 A6 Ex
W
G
AI05471
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M68AF127B
OPERATION
The M68AF127B has a Chip Enable power down feature which invokes an automatic standby mode whenever Chip Enable is de-asserted (E1 = High), or Chip Select is asserted (E2 = Low). An Output Enable (G) signal provides a high-speed, tri-state Read Mode The M68AF127B is in the Read mode whenever Write Enable (W) is High with Output Enable (G) Low, Chip Enable (E1) is asserted and Chip Select (E2) is de-asserted. This provides access to data from eight of the 1,048,576 locations in the static memory array, specified by the 17 address inputs. Valid data will be available at the eight output pins Write Mode The M68AF127B is in the Write mode whenever the W and E1 pins are Low and the E2 pin is High. Either the Chip Enable input (E1) or the Write Enable input (W) must be de-asserted during Address transitions for subsequent write cycles. Write begins with the concurrence of E1 being active with W low. Therefore, address setup time is referenced to Write Enable and Chip Enable as tAVWL and tAVEH, respectively, and is determined by the latter occurring edge. Table 2. Operating Modes
Operation Read Read Write Deselect Deselect
Note: X = VIH or VIL.
control, allowing fast read/write cycles to be achieved with the common I/O data bus. Operational modes are determined by device control inputs W and E1 as summarized in the Operating Modes table (Table 2).
within t AVQV after the last stable address, providing G is Low and E1 is Low. If Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter (tELQV or tGLQV) rather than the address. Data out may be indeterminate at tELQX and tGLQX, but data lines will always be valid at t AVQV.
The Write cycle can be terminated by the earlier rising edge of E1, or W. If the Output is enabled (E1 = Low, E2 = High and G = Low), then W will return the outputs to high impedance within tWLQZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. Data input must be valid for tDVWH before the rising edge of Write Enable, or for tDVEH before the rising edge of E1, whichever occurs first, and remain valid for tWHDX or tEHDX.
E1 VIL VIL VIL VIH X
E2 VIH VIH VIH X VIL
W VIH VIH VIL X X
G VIH VIL X X X
DQ0-DQ7 Hi-Z Data Output Data Input Hi-Z Hi-Z
Power Active (ICC) Active (ICC) Active (ICC) Standby (ISB) Standby (ISB)
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M68AF127B
MAXIMUM RATING
Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is Table 3. Absolute Maximum Ratings
Symbol IO
(1)
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Parameter Output Current Ambient Operating Temperature Storage Temperature Supply Voltage Input or Output Voltage Power Dissipation
Value 20 -55 to 125 -65 to 150 -0.5 to 6.5 -0.5 to VCC +0.5 1
Unit mA C C V V W
TA TSTG VCC VIO
(2)
PD
Note: 1. One output at a time, not to exceed 1 second duration. 2. Up to a maximum operating VCC of 6.0V only.
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M68AF127B
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measurement Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
Table 4. Operating and AC Measurement Conditions
Parameter VCC Supply Voltage Range 1 Ambient Operating Temperature Range 6 Load Capacitance (CL) Output Circuit Protection Resistance (R1) Load Resistance (R2) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages Output Transition Timing Ref. Voltages -40 to 85C 100pF 3.0k 3.1k 1ns/V 0 to VCC VCC/2 VRL = 0.3VCC; VRH = 0.7VCC M68AF127B 4.5 to 5.5V 0 to 70C
Figure 7. AC Measurement I/O Waveform
Figure 8. AC Measurement Load Circuit
VCC
I/O Timing Reference Voltage R1 VCC VCC/2 0V DEVICE UNDER TEST CL Output Transition Timing Reference Voltage VCC R2 0.7VCC 0.3VCC
AI04831
OUT
0V
CL includes JIG capacitance
AI05814
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M68AF127B
Table 5. Capacitance
Symbol CIN COUT Parameter (1,2) Input Capacitance on all pins (except DQ) Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 8 Unit pF pF
Note: 1. Sampled only, not 100% tested. 2. At TA = 25C, f = 1MHz, VCC = 3.0V.
Table 6. DC Characteristics
Symbol ICC1 (1,2) ICC2 (3) ILI ILO (4) ISB VIH VIL VOH VOL
Note: 1. 2. 3. 4.
Parameter Supply Current
Test Condition VCC = 5.5V, f = 1/tAVAV, IOUT = 0mA VCC = 5.5V, f = 1MHz, IOUT = 0mA 0V VIN VCC 0V VOUT VCC VCC = 5.5V, E1 VCC - 0.2V, E2 0.2V, f = 0 55 70
Min
Typ 7.5 6.0
Max 20 15 2
Unit mA mA mA A A A V V V
Operating Supply Current Input Leakage Current Output Leakage Current Standby Supply Current CMOS Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage
-1 -1 2.5 2.2 -0.3
1 1 15 VCC + 0.3 0.8
IOH = -1mA IOL = 2.1mA
2.4 0.4
V
Average AC current, cycling at tAVAV minimum. E1 = V IL, E2 = VIH, VIN = VIH or VIL. E1 0.2V or E2 V CC -0.2V, VIN 0.2V or VIN VCC -0.2V. Output disabled.
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M68AF127B
Figure 9. Address Controlled, Read Mode AC Waveforms
tAVAV A0-A16 tAVQV VALID tAXQX
DQ0-DQ7
DATA VALID
AI05474
Note: E1 = Low, E2 = High, G = Low, W = High.
Figure 10. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms
tAVAV A0-A16 tAVQV tELQV E1 VALID tAXQX tEHQZ
E2
tELQX tGLQV G tGLQX DQ0-DQ7 VALID
AI05476
tGHQZ
Note: Write Enable (W) = High.
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M68AF127B
Figure 11. Chip Enable Controlled, Standby Mode AC Waveforms
E1
E2 ICC ISB tPU 50%
AI05477
tPD
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M68AF127B
Table 7. Read and Standby Mode AC Characteristics
M68AF127B Symbol tAVAV tAVQV tAXQX (1) tEHQZ (2,3) tELQV tELQX (1) tGHQZ (2,3) tGLQV tGLQX (2) tPD tPU Read Cycle Time Address Valid to Output Valid Data hold from address change Chip Enable High to Output Hi-Z Chip Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition Chip Enable or UB/LB High to Power Down Chip Enable or UB/LB Low to Power Up Parameter 55 Min Max Min Max Max Min Max Max Min Max Min 55 55 5 20 55 5 20 25 5 55 0 70 70 70 5 25 70 5 25 35 5 70 0 ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Test conditions assume transition timing reference level = 0.3VCC or 0.7VCC. 2. At any given temperature and voltage condition, tGHQZ is less than tGLQX and tEHQZ is less than t ELQX for any given device. 3. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
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M68AF127B
Figure 12. Write Enable Controlled, Write AC Waveforms
tAVAV A0-A16 VALID tAVWH tAVEL E1 tELWH tWHAX
E2 tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
AI05478
tWHQX
Figure 13. Chip Enable Controlled, Write AC Waveforms
tAVAV A0-A16 VALID tAVEH tAVEL E1 tELEH tEHAX
E2 tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI05479
tWLEH
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M68AF127B
Table 8. Write Mode AC Characteristics
M68AF127B Symbol tAVAV tAVEH tAVEL tAVWH tAVWL tDVEH tDVWH tEHAX tEHDX tELEH tELWH tWHAX tWHDX tWHQX (1) tWLEH tWLQZ (1,2) tWLWH Write Cycle Time Address Valid to Chip Enable High Address valid to Chip Enable Low Address Valid to Write Enable High Address Valid to Write Enable Low Input Valid to Chip Enable High Input Valid to Write Enable High Chip Enable High to Address Transition Chip enable High to Input Transition Chip Enable Low to Chip Enable High Chip Enable Low to Write Enable High Write Enable High to Address Transition Write Enable High to Input Transition Write Enable High to Output Transition Write Enable Low to Chip Enable High Write Enable Low to Output Hi-Z Write Enable Low to Write Enable High Parameter 55 Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Max Min 55 45 0 45 0 25 25 0 0 45 45 0 0 5 45 20 45 70 70 60 0 60 0 30 30 0 0 60 60 0 0 5 60 20 60 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. At any given temperature and voltage condition, tWLQZ is less than tWHQX for any given device. 2. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
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M68AF127B
Figure 14. E1 Controlled, Low VCC Data Retention AC Waveforms
DATA RETENTION MODE 5.5V VCC 4.5V
VDR > 2.0V tCDR E1 VDR - 0.2V E1 tR
AI07204
Figure 15. E2 Controlled, Low VCC Data Retention AC Waveforms
DATA RETENTION MODE 5.5V VCC 4.5V
VDR > 2.0V tCDR E2 0.2V E2 tR
AI07205B
Table 9. Low VCC Data Retention Characteristics
Symbol ICCDR (1) Parameter Supply Current (Data Retention) Test Condition VCC = 2.0V, E1 VCC -0.2V or E2 0.2V, f = 0 0 tAVAV E1 VCC -0.2V or E2 0.2V, f = 0 2.0 Min Max 4.5 Unit A ns ns V
tCDR (1,2) Chip Deselected to Data Retention Time tR
(2)
Operation Recovery Time Supply Voltage (Data Retention)
VDR (1)
Note: 1. All other Inputs at V IH VCC -0.2V or VIL 0.2V. 2. Tested initially and after any design or process that may affect these parameters. tAVAV is Read cycle time. 3. No input may exceed VCC +0.2V.
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M68AF127B
PACKAGE MECHANICAL
Figure 16. SO32 - 32 lead Plastic Small Outline, Package Outline
D
16 1
E
E1
17
32
A2 B SO-C e A1 CP
A C L1 L
Note: Drawing is not to scale.
Table 10. SO32 - 32 lead Plastic Small Outline, Package Mechanical Data
millimeters Symbol Typ B A A1 A2 C CP D E E1 e L L1 N 1.27 20.14 11.18 13.87 - 0.58 1.19 32 0.10 2.57 0.15 2.82 0.30 0.10 20.75 11.43 14.38 - 0.99 1.60 0.050 0.793 0.440 0.546 - 0.023 0.047 32 Min 0.36 Max 0.51 3.00 0.004 0.101 0.006 0.111 0.012 0.004 0.817 0.450 0.566 - 0.039 0.063 Typ Min 0.014 Max 0.020 0.118 inches
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M68AF127B
Figure 17. PDIP32 - 32 pin Plastic DIP, 600 mils width, Package Outline
A2 A1 b1 b D2 D S
N
A L
e
eA
c
E1
1
E
PDIP-C
Note: Drawing is not to scale.
Table 11. PDIP32 - 32 pin Plastic DIP, 600 mils width, Package Mechanical Data
millimeters Symbol Typ A A1 A2 b b1 c D eA e E E1 L S N 15.24 2.54 3.81 0.41 1.14 0.23 41.78 - - 15.24 13.46 3.05 1.65 0 32 0.53 1.65 0.38 42.29 - - 15.88 13.97 3.56 2.21 15 0.600 0.100 0.38 0.150 0.016 0.045 0.009 1.645 - - 0.600 0.530 0.120 0.065 0 32 0.021 0.065 0.015 1.665 - - 0.625 0.550 0.140 0.087 15 Min Max 4.83 0.015 Typ Min Max 0.190 inches
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M68AF127B
Figure 18. TSOP32 - 32-lead Thin Small Outline Package, 8x13.4mm, Package Outline
A2
1 N
e E B
N/2
D1 D
A CP
DIE
C
TSOP-a
Note: Drawing is not to scale.
A1
L
Table 12. TSOP32 - 32-lead Thin Small Outline Package, 8x13.4mm, Package Mechanical Data
millimeters Symbol Typ A A1 A2 B C CP D D1 E e L N 13.40 11.80 8.00 0.50 - - - - 0.40 0 32 0.22 0.10 0.21 0.10 - - - - 0.60 5 0.5276 0.4646 0.3150 0.0197 - - - - 0.0157 0 32 0.05 0.91 Min Max 1.20 0.15 1.05 0.0087 0.0039 0.0083 0.0039 - - - - 0.0236 5 0.0020 0.0358 Typ Min Max 0.0472 0.0059 0.0413 inches
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M68AF127B
Figure 19. TSOP32 - 32 lead Plastic Thin Small Outline, 8x20mm, Package Outline
A2
1 N
e E B
N/2
D1 D
A CP
DIE
C
TSOP-a
Note: Drawing is not to scale.
A1
L
Table 13. TSOP32 - 32 lead Plastic Thin Small Outline, 8x20mm, Package Mechanical Data
millimeters Symbol A A1 A2 B C CP D D1 e E L N 0.500 19.800 18.300 - 7.900 0.500 0 32 0.050 0.950 0.170 0.100 Typ Min Max 1.200 0.150 1.050 0.250 0.210 0.100 20.200 18.500 - 8.100 0.700 5 0.0197 0.7795 0.7205 - 0.3110 0.0197 0 32 0.0020 0.0374 0.0067 0.0039 Typ inches Min Max 0.0472 0.0059 0.0413 0.0098 0.0083 0.0039 0.7953 0.7283 - 0.3189 0.0276 5
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M68AF127B
PART NUMBERING
Table 14. Ordering Information Scheme
Example: Device Type M68 Mode A = Asynchronous Operating Voltage F = 4.5 to 5.5V Array Organization 127 = 1Mbit (128K x8) Option 1 B = 2 Chip Enable Option 2 L = L-Die M = M-Die Speed Class 55 = 55ns 70 = 70ns Package MC = SO32 B = PDIP32 NK = TSOP32 8x13.4mm N = TSOP32 8x20mm Operative Temperature 1 = 0 to 70C 6 = -40 to 85C Shipping T = Tape & Reel Packing M68AF127 B L 55 MC 6 T
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
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M68AF127B
REVISION HISTORY
Table 15. Document Revision History
Date August 2001 18-Oct-2001 29-Nov-2001 06-Mar-2002 17-May-2002 31-May-2002 Version 1.0 2.0 3.0 4.0 5.0 6.0 First Issue. SO32 Package Mechanical and Data added (Figure 1, 3 and 16, Table 10). Note removed from Ordering Information Scheme. Document status changed to Data Sheet. Document globally revised. PDIP32 Package added (Figure 1, 4 and 17, Table 11). Chip Enable Low VCC Data Retention clarified (Figure 14 and 15, Table 9). TSOP32 8x13.4mm and TSOP32 8x20mm packages added (Figure 1, 5, 18 and 19, Table 12, 13 and 14). Commercial code clarified. Title and header layout modified. Datasheet number simplified. Label corrected on "E2 Controlled, Low VCC Data Retention AC Waveforms" figure. TSOP Package connections modified (Figure 5). Test conditions for ICCDR modified in Table 9, Low VCC Data Retention Characteristics. TSOP Package connections modified (Figure 5). Document structure modified: - Chapter OPERATION moved before chapter MAXIMUM RATING. - AC Characteristics Tables and waveforms moved to the DC/AC PARAMETERS section. tPU ad tPD updated in Table 7. Revision Details
09-Sep-2002 02-Oct-2002 09-Oct-2002 16-Apr-2003 08-Aug-2003 21-Aug-2003
6.1 6.2 6.3 6.4 6.5 6.6
24-Sep-2004
7
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M68AF127B
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